Math2Mat aims at automatically generating a VHDL description of a mathematical description written in Octave/Matlab. The generation creates a synthesizable RTL description using floating point operators (32 or 64 bits) combined in a fully pipelined way. Emphasis is put on the throughput attainable by the design, especially in the ”for loop” implementation. The software also offers a graphical user interface, letting the developer manage the different parameters before generation. Verification can also be launched from the software, a SystemVerilog testbench being automatically generated.
Titre
Math2Mat : from Octave/Matlab to VHDL
Date
2012-06
Publié dans
Proceedings of 2012 NASA/ESA Conference on Adaptive Hardware and Systems (AHS), 25-28 June 2012, Erlangen, Germany
Editeur
Erlangen, Germany, 25-28 June 2012
Pagination
8 p.
Présenté à
2012 NASA/ESA Conference on Adaptive Hardware and Systems (AHS), Erlangen, Germany, 2012-06-25, 2012-06-28
ISBN
978-1-4673-1916-4
Type de papier
full paper
Domaine
Ingénierie et Architecture
Ecole
HEIA-FR
HEPIA - Genève
HE-Arc Ingénierie
HEI-VS
HEIG-VD
Institut
Institut Systèmes industriels
iSIS - Institut des systèmes intelligents et sécurisés
ReDS - Reconfigurable & embedded Digital Systems