Math2Mat : from Octave/Matlab to VHDL

Thoma, Yann (School of Management and Engineering Vaud, HES-SO // University of Applied Sciences Western Switzerland) ; Messerli, Etienne (School of Management and Engineering Vaud, HES-SO // University of Applied Sciences Western Switzerland) ; Starkier, Michel (School of Management and Engineering Vaud, HES-SO // University of Applied Sciences Western Switzerland) ; Molla, Daniel (School of Management and Engineering Vaud, HES-SO // University of Applied Sciences Western Switzerland) ; Masle, Sébastien (School of Management and Engineering Vaud, HES-SO // University of Applied Sciences Western Switzerland) ; Bianchi, Christophe (School of Engineering, HES-SO Valais-Wallis, HEI, HES-SO // University of Applied Sciences Western Switzerland) ; Gubler, Oliver (School of Engineering, HES-SO Valais-Wallis, HEI, HES-SO // University of Applied Sciences Western Switzerland) ; Magliocco, Claude (School of Engineering and Architecture (HEIA-FR), HES-SO // University of Applied Sciences Western Switzerland) ; Crausaz, Philippe (School of Engineering and Architecture (HEIA-FR), HES-SO // University of Applied Sciences Western Switzerland) ; Tâche, Samuel (School of Engineering and Architecture (HEIA-FR), HES-SO // University of Applied Sciences Western Switzerland) ; Prêtre, Denis (School of Engineering – HE-Arc Ingénierie, HES-SO // University of Applied Sciences Western Switzerland) ; Trolliet, Gregory (School of Engineering, Architecture and Landscape (hepia), HES-SO // University of Applied Sciences Western Switzerland)

Math2Mat aims at automatically generating a VHDL description of a mathematical description written in Octave/Matlab. The generation creates a synthesizable RTL description using floating point operators (32 or 64 bits) combined in a fully pipelined way. Emphasis is put on the throughput attainable by the design, especially in the ”for loop” implementation. The software also offers a graphical user interface, letting the developer manage the different parameters before generation. Verification can also be launched from the software, a SystemVerilog testbench being automatically generated.


Mots-clés:
Type de conférence:
full paper
Faculté:
Ingénierie et Architecture
Ecole:
HEIA-FR
HEPIA - Genève
HE-Arc Ingénierie
HEI-VS
HEIG-VD
Institut:
Institut Systèmes industriels
iSIS - Institut des systèmes intelligents et sécurisés
ReDS - Reconfigurable & embedded Digital Systems
Classification:
Ingénierie
Adresse bibliogr.:
Erlangen, Germany, 25-28 June 2012
Date:
2012-06
Erlangen, Germany
25-28 June 2012
Pagination:
8 p.
Publié dans:
Proceedings of 2012 NASA/ESA Conference on Adaptive Hardware and Systems (AHS), 25-28 June 2012, Erlangen, Germany
DOI:
ISBN:
978-1-4673-1916-4
Le document apparaît dans:

Note: The status of this file is: restricted


 Notice créée le 2019-04-02, modifiée le 2020-10-27

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