Capacitor voltage ripple minimization in voltage source converter for HVDC applications

Marchesoni, Mario (DITEN - Polytechnic School, Unviersity of Genova, Genova, Italy) ; Passalacqua, Massimiliano (DITEN - Polytechnic School, Unviersity of Genova, Genova, Italy) ; Vaccaro, Luis (DITEN - Polytechnic School, Unviersity of Genova, Genova, Italy) ; Carpita, Mauro (School of Management and Engineering Vaud, HES-SO // University of Applied Sciences Western Switzerland) ; Gavin, Serge (School of Management and Engineering Vaud, HES-SO // University of Applied Sciences Western Switzerland) ; Kissling, Simon (School of Management and Engineering Vaud, HES-SO // University of Applied Sciences Western Switzerland)

Keywords:
Conference Type:
full paper
Faculty:
Ingénierie et Architecture
School:
HEIG-VD
Institute:
IESE - Institut d'Energie et Systèmes Electriques
Publisher:
Florence, Italy, 9-10 May 2019
Date:
2019-06
Florence, Italy
9-10 May 2019
Pagination:
6 p.
Published in:
Proceedings of 2019 AEIT HVDC International Conference (AEIT HVDC), 9-10 May 2019, Florence, Italy
DOI:
ISBN:
978-1-7281-2071-3
Appears in Collection:

Note: The status of this file is: restricted


 Record created 2019-11-26, last modified 2020-10-27

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