Fault mitigation by means of dynamic partial reconfiguration of virtex-5 FPGAs

Curchod, Gilles (School of Management and Engineering Vaud, HES-SO // University of Applied Sciences Western Switzerland) ; Upegui, Andres (School of Engineering, Architecture and Landscape (hepia), HES-SO // University of Applied Sciences Western Switzerland) ; Izui, Julien (School of Engineering, Architecture and Landscape (hepia), HES-SO // University of Applied Sciences Western Switzerland)

This paper presents a technique to mitigated SEU faults on Virtex-5 FPGAs through the use of dynamic partial reconfiguration. The key idea is to reconfigure the damaged part of the configuration bitstream in order to repair the bitstream and, thus, the overlying architecture. To this end, we propose a design flow and a set of tools that allow us to manipulate the bitstream generation. As case study, we present an application using an AES encryption coprocessor, a fault detection system constantly verifying system integrity and repairing faults, and an independent program injecting faults to validate the system.


Keywords:
Conference Type:
full paper
Faculty:
Ingénierie et Architecture
School:
HEPIA - Genève
HEIG-VD
Institute:
inIT - Institut d'Ingénierie Informatique et des Télécommunications
ReDS - Reconfigurable & embedded Digital Systems
Publisher:
Cancun, Mexico, 5-7 December 2012
Date:
2012-12
Cancun, Mexico
5-7 December 2012
Pagination:
6 p.
Published in:
Proceedings of 2012 International Conference on Reconfigurable Computing and FPGAs, 5-7 December 2012, Cancun, Mexico
DOI:
ISBN:
978-1-4673-2921-7
Appears in Collection:

Note: The status of this file is: restricted


 Record created 2020-07-03, last modified 2020-07-14

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