FPGA partial reconfiguration in software Defined radio devices

Grassi, Sara (School of Management and Engineering Vaud, HES-SO // University of Applied Sciences Western Switzerland) ; Convers, Anthony (School of Management and Engineering Vaud, HES-SO // University of Applied Sciences Western Switzerland) ; Dassatti, Alberto (School of Management and Engineering Vaud, HES-SO // University of Applied Sciences Western Switzerland)

Many SDR systems make effective use of FPGAs for data acquisition and heavy lifting DSP processing. This has resulted in several dedicated frameworks being developed, RFNoC being the most renowned. Even though FPGAs fabrics are, by their nature, reconfigurable, SDR systems often fail in exploiting this interesting opportunity at run-time. In this paper, we show how it is possible to make effective use of the Partial Reconfiguration capabilities of modern FPGA devices, extending the range of applications RFNoC can be applied to. In particular, it allows the live reconfiguration of signal processing chains, for instance to switch between wireless standards. This results in a better use of the limited FPGA resources by time-sharing them between processing blocks. Unfortunately, support for Partial Reconfiguration is not yet available in the software stack of commercially-available SDR devices. Our work thus aims at encouraging its integration.


Conference Type:
full paper
Faculty:
Ingénierie et Architecture
School:
HEIG-VD
Institute:
ReDS - Reconfigurable & embedded Digital Systems
Publisher:
Charlotte, NC, USA, 14-18 September 2020
Date:
2020-09
Charlotte, NC, USA
14-18 September 2020
Pagination:
7 p.
Published in:
Proceedings of the 10th GNU Radio Conference, 14-18 September 2020, Charlotte, North Carolina, USA
Numeration (vol. no.):
2020, vol. 5, no. 1
Appears in Collection:



 Record created 2020-10-06, last modified 2020-10-27

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