A FPGA-based post-processing and validation platform for random number generators

Gentel, Laurent (School of Engineering, Architecture and Landscape (hepia), HES-SO // University of Applied Sciences Western Switzerland) ; Duc, Alexandre (School of Management and Engineering Vaud, HES-SO // University of Applied Sciences Western Switzerland) ; Steiner, Lucie (School of Management and Engineering Vaud, HES-SO // University of Applied Sciences Western Switzerland) ; Vannel, Fabien (School of Engineering, Architecture and Landscape (hepia), HES-SO // University of Applied Sciences Western Switzerland) ; Upegui, Andres (School of Engineering, Architecture and Landscape (hepia), HES-SO // University of Applied Sciences Western Switzerland) ; Gluck, Florent (School of Engineering, Architecture and Landscape (hepia), HES-SO // University of Applied Sciences Western Switzerland)

Cryptography and computer security rely heavily on random numbers for key exchange of authentication algorithms. However, current Internet-of-Things (IoT) device security is often based on poor quality pseudo-random number generators (PRNGs). This issue can be overcome using true random number generators (TRNGs) that may offer better quality and higher security. Nonetheless, TRNG often provide slow throughput and require post-processing to correct hardware biases and ensure the desired statistical behavior. In this paper, we present a FPGA-based hardware platform able to validate and post-process multiple TRNG sources. Moreover, we propose a hardware implementation of a provably secure post-processing algorithm called SPRG. Based on the sponge construction and the Keccak-f standard, it improves random number quality while maintaining high data throughput. A full platform providing hardware acceleration has been implemented on a Xilinx Kintex- 7 FPGA board to test the validity of the generated numbers through χ 2 and SP800-90B online statistical tests, and to improve the randomness using AIS-31 or SPRG post-processing hardware cores. The proposed platform is modular and targets both IoT edge devices and back-end servers.


Keywords:
Conference Type:
published full paper
Faculty:
Ingénierie et Architecture
School:
HEPIA - Genève
HEIG-VD
Institute:
IICT - Institut des Technologies de l'Information et de la Communication
inIT - Institut d'Ingénierie Informatique et des Télécommunications
Publisher:
New Orleans, USA, 18-22 May 2020
Date:
2020-05
New Orleans, USA
18-22 May 2020
Pagination:
4 p.
Published in:
Proceedings of 2020 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW), 18-22 May 2020, New Orleans, USA
DOI:
ISBN:
978-1-7281-7445-7
Appears in Collection:

Note: The status of this file is: restricted


 Record created 2021-02-09, last modified 2021-02-12

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