Enabling optimal power generation of flow cell arrays in 3D MPSoCs with on-chip switched capacitor converters

Najibi, Halima (EPFL, Lausanne, Switzerland) ; Hunter, Jorge (Centro de Electronica Industrial, UPM, Spain) ; Levisse, Alexandre (EPFL, Lausanne, Switzerland) ; Zapater, Marina (EPFL, Lausanne, Switzerland ; School of Management and Engineering Vaud, HES-SO // University of Applied Sciences Western Switzerland) ; Vasic, Miroslav (Centro de Electronica Industrial, UPM, Spain) ; Atienza, David (EPFL, Lausanne, Switzerland)

Flow cell arrays (FCAs) provide efficient on-chip liquid cooling and electrochemical power generation capabilities in three-dimensional multi-processor systems-on-chip (3D MPSoCs). When connected to power delivery networks (PDNs) of chips, the current flowing between FCA electrodes partially supplies logic gates and compensates over 20% Vdd drop in high-performance 3D systems. However, operation voltages of CMOS technologies are generally higher than the voltage corresponding to the maximal FCA power generation. Hence, directly connecting FCAs to 3D MPSoC power grids results in sub-optimal performance. In this paper, we design an on-chip direct current to direct current (DC-DC) converter to improve FCA power generation in high-performance 3D MPSoCs. We use switched capacitor (SC) technology and explore different design space parameters to achieve minimal area requirement and maximal power extraction. The proposed converter enables a stable and optimal voltage between FCA electrodes. Furthermore, it allows us to dynamically control FCA connectivity to 3D PDNs, and switch off power extraction during chip inactivity. We show that regulated FCAs generate up to 123% higher power with respect to the case they are directly connected to 3D PDNs. In addition, connecting multiple flow cells to a single optimized converter reduces area requirement down to 1.26%, while maintaining IR-drop below 5%. Finally, we show that activity-based dynamic FCA switching extends by over 1.8X and 4.5X electrolytes lifetime for a processor duty-cycle of 50% and 20%, respectively.


Keywords:
Conference Type:
published full paper
Faculty:
Ingénierie et Architecture
School:
HEIG-VD
Institute:
ReDS - Reconfigurable & embedded Digital Systems
Publisher:
Limassol, Cyprus, 6-8 July 2020
Date:
2020-07
Limassol, Cyprus
6-8 July 2020
Pagination:
6 p.
Published in:
Proceedings of 2020 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 6-8 July 2020, Limassol, Cyprus
DOI:
ISBN:
978-1-7281-5775-7
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 Record created 2021-04-06, last modified 2021-04-07

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