Powerful channel codes are employed in modern communication systems in order to achieve very high data rates over noisy channels. The extremely low bit error rate (BER) reached by these codes requires that a huge number of samples are simulated to validate the system design. In addition simulation time is often made excessively long by the high computational complexity of addressed decoding algorithms and by the need of exploring the effect of code performance of different implementation choices (including finite precision representation of input and internal data), channel noise, fading and interferences. The use of software simulators may result in unacceptably long times and more cost effective solutions are required. This paper describes the design and the implementation of a new platform for accelerating channel codes simulations: a novel approach based on a mixed hardware-software design is described. The proposal ensures a wide range of flexibility and a significant reduction of the simulation time exploiting modern FPGAs characteristics.