Next-generation High-Performance Computing (HPC) systems need to provide outstanding performance with unprecedented energy efficiency while maintaining servers at safe thermal conditions. Air cooling presents important limitations when employed in HPC infrastructures. Instead, two-phase onchip cooling combines small footprint area and large heat exchange surface of micro-channels together with extremely high heat transfer performance, and allows for waste heat recovery. When relying on gravity to drive the flow to the heat sink, the system is called a closed-loop two-phase thermosyphon. Previous research work either focused on the development of large-scale proof-of-concept thermosyphon demonstrators, or on the development of numerical models able to simulate their operation. In this work, we present a new ultra-compact microscale thermosyphon design for high heat flux components. We manufactured a working 8 cm height prototype tailored for Virtex 7 FPGAs with a heat spreader area of 45 mm × 45 mm, and we validate its performance via measurements. The results are compared to our simulator and accurately match the thermal performance of the thermosyphon, with error of less than 3.5% . Our prototype is able to work over the full range of power of the Virtex7, dissipating up to 60 W of power while keeping chip temperature below 60°C. The prototype will next be deployed in a 10 kW rack as part of an HPC prototype, with an expected Power Usage Effectiveness (PUE) below 1.05.