This paper presents the system-level simulation platform we have implemented to design and evaluate the SORU reconfigurable vector coprocessor, aimed at enhancing the security of embedded systems. The simulator interfaces a lowlevel virtual machine (LLVM) with a SystemC TLM 2.0 model of the rest of the system, and a low-level SystemC model of the coprocessor. The results show that we can simulate more than 80K coprocessor operations per second, with decent power estimation, that allows to perform simulated power analysis attacks. The resulting simulation platform is also flexible enough to allow very fast and easy changes to any part of the system.